(1) Field of the Invention
The present invention relates to a ball grid array semiconductor device where a terminal arrangement is an area array, and a manufacturing method thereof.
(2) Description of the Related Art
Recently, with respect to electronic equipment, particularly, portable equipment, there are increasing demands for multifunction, high performance, space saving, and low cost. In response to this trend, a semiconductor element having multiple pins arranged thereon at a fine pitch and having a shrunk chip size becomes popular.
Consequently, development of a package including the semiconductor element having the aforementioned features so as to satisfy the aforementioned demands becomes urgent. As for development of a package, a pitch between terminals is made finer by a multipin-type QFP; thus, space saving is achieved.
However, in order to achieve still further space saving, there is developed a ball grid array package (hereinafter, simply referred to as “BGA”) where an arrangement of terminals TS1 is an area array as illustrated in FIG. 7 (refer to, e.g., Japanese Unexamined Utility Model Publication No. 1-332). As a result, there is an increasing demand for the BGA.
Size reduction by space saving is especially required for such a BGA. As one of methods for realizing size reduction, electrodes connected to metal nanowires of an interposer are arranged at a fine pitch.
However, if the electrodes are arranged at a fine pitch, a wire bonding apparatus is degraded in accuracy of recognizing the electrodes. As a result, there is a possibility that positional deviation upon bonding occurs. In order to avoid this disadvantage, as illustrated in FIG. 8, recognition patterns NP1 having a specific shape different from that of an electrode are arranged at corners of an interposer IP1 having electrodes arranged thereon in four directions in order to improve recognition accuracy; thus, positional deviation upon bonding is prevented.
However, this conventional technique has the following problems.
In future, still further cost reduction is required for a BGA; therefore, it is important to design an interposer such that semiconductor devices to be obtained from one substrate 17 illustrated in FIG. 7 are increased in number. In order to increase semiconductor devices to be obtained from one substrate 17 in number, it is indispensable that an interposer is effectively arranged to eliminate a wasteful space from which no semiconductor device is obtained.
Consequently, a dimension of a recognition pattern 18 arranged at the wasteful space from which no semiconductor device is obtained must be decreased. In addition, as a BGA is reduced in outer dimension, a corner space for electrodes arranged on an interposer in four directions becomes narrow, so that a recognition pattern is reduced in size.
A wire bonding apparatus fails to recognize such a recognition pattern having a reduced size, so that positional deviation upon bonding occurs. This means that electrodes of an interposer cannot be arranged at a fine pitch, leading to hindrance to size reduction of a semiconductor device.
In a die bonding process, the recognition patterns NP1 are used as recognition marks for alignment. Therefore, if recognition accuracy is degraded due to small recognition marks, accuracy of mounting a semiconductor element on a substrate is also degraded. This means that a distance between a side face of a semiconductor element and an electrode of an interposer cannot be made short, leading to hindrance to size reduction of a semiconductor device.